The present invention relates to an integrated circuit device, and more particularly, to integrated circuit devices having internal voltage generation circuits therein.
As the integration density of integrated circuits continues to increase, the size of some elements present in those circuits, such as transistors, may decrease. However, as the size of some of the transistors present in those integrated circuits decreases, new methods for ensuring the stability of those integrated circuits may become necessary. For example, when the same external supply voltage is applied to both large and small transistors present in an integrated circuit memory device, electric fields within the integrated circuit memory device may cause smaller transistors to either malfunction or breakdown. This phenomenon may be prevented by decreasing an external supply voltage that is used to operate the memory device. To decrease the external supply voltage an internal voltage generation circuit may be used. Integrated circuit memory devices including these internal voltage generation circuits may exhibit improved stability while consuming less power in comparison to integrated circuit memory devices that use only an external supply voltage to control supply voltage.
FIG. 1 is a diagram showing a conventional internal voltage generation circuit. The internal voltage generation circuit includes a differential amplifier 10 and a driver 20. The differential amplifier 10 compares a reference voltage VREF with an internal supply voltage VINT, and generates an output voltage VA depending on the result of the comparison. The reference voltage VREF has a fixed voltage level with respect to an external supply voltage VCC. The driver 20 generates the internal supply voltage VINT in response to the output voltage VA of the differential amplifier 10.
During the operation of the internal voltage generation circuit, the internal supply voltage VINT is preferably set to have the same voltage level as the reference voltage VREF. When the internal supply voltage VINT is reduced to a level below the reference voltage VREF, the output voltage VA of the differential amplifier 10 is also lowered and the transistor MP2 of the driver 20 is turned on to a greater extent. Turning on MP2 to a greater extent operates to pull-up the internal supply voltage VINT signal line until the internal supply voltage VINT is equal to the reference voltage VREF. When the internal supply voltage VINT is equal to the reference voltage, the differential amplifier 10 achieves a quiescent operating point.
Transistors MNO and MN1 preferably operate in a saturation region during operation of the differential amplifier 10. In other words, when the voltage level of the internal supply voltage VINT drops, for example, due to a load on the internal supply voltage VINT, the differential amplifier 10 restores the voltage level of the internal supply voltage VINT to the original voltage level, which is preferably equal to the reference voltage VREF.
However if VCC, VREF, and VINT are reduced in order to reduce power consumption, then the voltage VDS of the transistors MN0 and MN1 becomes smaller. This may cause the transistors MN0 and MN1, which are set to operate in a saturation region S1, to begin to operate in a linear region L1. As shown in the IDS vs. VDS curves of FIG. 2, when the voltage VDS of the transistors MN0 and MN1 becomes smaller, the operating points of the transistors MN0 and MN1 shift from the saturation region S1 into a linear region L1 of operation. The gain of the transistors MN0 and MN1 in the saturation region can be expressed as:                               g          m                =                              ∂                          I              DS                                            ∂                          V              GS                                                          (        1        )            
Assuming that the gain of MN0, MN1 in the saturation region S1 is expressed as gmS1, and that the gain in the linear region L1 is expressed as gmL1, then the gmS1 greater than gmL1 due to current IDS decreasing as the operating points of the transistors MN0 and MN1 shift to the linear region. However, the VDS may remain constant. Since the gain in the linear region is smaller, the differential amplifier 10 may not be capable of accurately adjusting VINT to match VREF during normal operating modes when the driver 20 is supplying current to the VINT signal line.
Accordingly, there is a need for internal voltage generation circuits that can generate a stable internal supply voltage at low external supply voltage without loss of gain in the differential amplifier stage of the internal voltage generation circuit.
Accordingly, the present invention provides internal voltage generation circuits which can steadily generate an internal supply voltage even if an external supply voltage decreases. A level shifter is connected to an internal supply voltage terminal. The level shifter lowers the internal supply voltage to a predetermined voltage level. A differential amplifier compares an output voltage of the internal voltage generation circuit to an output voltage of the level shifter and amplifies the difference between the two output voltages. A driver generates an internal supply voltage in response to an amplifier output of the differential amplifier. The internal voltage generation circuit preferably includes a second level shifter, which is connected to a reference voltage terminal. The second level shifter preferably lowers a reference voltage to a predetermined voltage level. In this case, the output voltage of the internal voltage generation circuit is an output voltage of the second level shifter. The differential amplifier may then compare the output voltage of the second level shifter to the output voltage of the first level shifter and amplify the difference between the two output voltages.
The first and second level shifters preferably comprise source followers and can decrease the internal supply voltage and the reference voltage, respectively, by a threshold voltage. More specifically, the first level shifter preferably includes a first transistor, in which an internal supply voltage is applied to the gate. The external supply voltage can be applied to the drain, and the source can be connected to the differential amplifier. A first current source may also be included, which is connected to the source of the first second transistor and ground. The second level shifter can include a second transistor in which the reference voltage can be applied to the gate. The external supply voltage may be applied to the drain, and the source can be connected to the differential amplifier. A second current source may be connected to the source of the second transistor and ground.
Internal voltage generation circuits according to the present invention may also include a current source controller for maintaining a constant current flowing in the current sources. The current source controller preferably includes a voltage bias unit for setting a predetermined voltage level, and a current mirror to which the external supply voltage can be applied. The current mirror determines the current volume of the current source based on the voltage level of the voltage bias unit.
According to other embodiments of the present invention internal voltage generators are provided that include a differential amplifier, a driver circuit, and a first level shifter circuit. The differential amplifier has first and second inputs. The driver circuit has an input electrically coupled to a first output of the differential amplifier, and an output electrically coupled to an internal voltage signal line. For example, the driver circuit can comprise a PMOS transistor having a gate electrode electrically connected to the first output of the differential amplifier and a drain electrically connected to the internal voltage signal line. The first level shifter circuit has an input electrically coupled to the internal voltage signal line, and an output electrically coupled to the first input of the differential amplifier. These internal voltage generators may also include a second level shifter circuit. Preferably, the second level shifter has an input electrically coupled to a reference voltage signal line and an output electrically coupled to the second input of said differential amplifier.
The first and second level shifter circuits may preferably comprise first and second source followers, respectively. For instance, the first source follower may include a first NMOS transistor and a current source. The first NMOS transistor preferably has a gate electrode electrically connected to the internal voltage signal line and a source electrically connected to the first input of the differential amplifier. The current source is preferably electrically connected to the source of the first NMOS transistor.
According to other embodiments of the present invention internal voltage generators are provided that include a differential amplifier, a PMOS transistor, and a first NMOS transistor, a first current source, a second NMOS transistor, and a second current source. The PMOS transistor preferably has a gate electrode electrically connected to a first output of said differential amplifier, a source electrically connected to a power supply signal line and a drain electrically connected to an internal voltage signal line. The first NMOS transistor preferably has a gate electrode electrically connected to the internal voltage signal line, a drain electrically connected to the power supply signal line and a source electrically connected to a first input of said differential amplifier. The first current source may have a first terminal electrically connected to the source of the first NMOS transistor. The second NMOS transistor preferably has a gate electrode electrically connected to a reference voltage signal line, a drain electrically connected to the power supply signal line and a source electrically connected to a second input of said differential amplifier. The second current source can have a first terminal electrically connected to the source of said second NMOS transistor. The generator may also include a current source controller electrically connected to second terminals of said first and second current sources, for example, a current mirror.
According to other embodiments of the present invention internal voltage generation circuits are provided that include a first level shifter, a differential amplifier, and a driver. The first level shifter can be connected to an internal supply voltage terminal that lowers an internal supply voltage to a predetermined voltage level. The differential amplifier may be connected to the first level shifter that comprises a reference voltage to an output voltage of the first level shifter and amplifies the difference between the reference voltage and the output voltage. The driver that preferably generates an internal supply voltage in response to an amplifier output of the differential amplifier. These internal voltage generation circuits may also include a second level shifter connected to a reference voltage terminal that lowers a reference voltage to a predetermined voltage level. In this case, the output voltage of the internal voltage generation circuit is an output voltage of the second level shifter. The differential amplifier compares the output voltage of the second level shifter to the output voltage of the first level shifter and amplifies the difference between the two output voltages. The first and second level shifters preferably decrease the internal supply voltage and the reference voltage, respectively, by a threshold voltage.
Each of the first and second level shifters can comprise a source follower. For instance, the first level shifter can include a second transistor and a second current source, while the second level shifter may include a first transistor and a first current source. In the first transistor, the reference voltage is applied to the gate, the external supply voltage is applied to the drain, and the source is connected to the differential amplifier. The first current source connected to the source of the transistor and ground. In the second transistor, the internal supply voltage is applied to the gate, the external supply voltage is applied to the drain, and the source is connected to e differential amplifier. The second current source is preferably connected to the source of the transistor and ground. These internal voltage generation circuits may further include a current source controller that maintains a constant current flowing in the first and second current sources. The current source controller preferably comprises a voltage bias unit that sets a predetermined voltage level, and a current mirror to which the external supply voltage is applied that determines the current volume of the current source based on the voltage level of the voltage bias unit.
The internal voltage generation circuit of the present invention can stably generate the internal supply voltage even if the level of the external supply voltage is lowered. The internal voltage generation circuit may also restore the level of the internal supply voltage to its original level equal to the reference voltage, even when the level of the internal supply voltage drops due to a load or when undershooting or overshooting occurs. In addition, the internal voltage generation circuit of the present invention can operate with a current consumption similar to conventional internal voltage generation circuits.